1. Field of the Invention
The present invention relates to a surge absorber and a surge absorber array, and more particularly to a surge absorber and a surge absorber array for absorbing and removing a surge voltage which enters a signal line.
2. Description of the Related Art
Generally, electronic components, such as ICs, which are susceptible to an incoming surge voltage include a surge absorber using a discharge element. Such a surge absorber is typically mounted between a signal line and a ground on a printed board.
As disclosed in Japanese Examined Utility Model Registration Application Publication No. 63-45749 and Japanese Unexamined Patent Application Publication No. 1-102884, a two-terminal surge absorber in which a laminated compact of ceramic sheets includes a pair of internal electrodes and a discharge hole is known in the related art.
When such a two-terminal surge absorber is mounted on a printed board, the ground wiring on the printed board gets complicated and a large mounting space is required. So miniaturization of devices is difficult to achieve.
This type of surge absorber uses a combination of a discharge element and a resistance element. When a discharge element is used alone, it is generally difficult to obtain a discharge element having a low discharge-starting voltage, because the discharge must start at a voltage below the breakdown voltage of the IC in order to protect the IC.
In the related art, the discharge element and the resistance element are configured as separate components, however, and it takes substantial time and labor to mount the components on a printed board, which increases the manufacturing cost and the required space for mounting.
Japanese Unexamined Patent Application Publication No. 5-6810 discloses a chip varistor with a resistor. However, a varistor generally has a capacitance of several picofarads to several hundred picofarads due to its material and structure, so it cannot be used in a high-speed signal processing circuit because the signal wave is rounded.